1. UETRV_Pcore: User Guide

1.1. Getting Started

Install RISC-V toolchain and verilator. These tools can be built by following the instructions in the corresponding links, or can be installed directly by running the following command

sudo apt-get install -y gcc-riscv64-unknown-elf verilator gtkwave

Check that these tools are installed correctly, by running verilator --version and riscv64-unknown-elf-gcc -v.

1.1.1. Build Model and Run Simulation

Verilator model of Pcore can be built using Makefile:

make verilate

The verilator model is build under ver_work/Vpcore_sim. The executeable can accept the following three parameters:

• imem : This paramerter accepts the file that contain the hexadecimal instructions of compiled program.

• max_cycles: This parameter cotrols the maxiumum number of cycles for simulation. Simulation terminates after executing these many cycles.

• vcd: This parameters accepts a boolean value. If it is 0, the waveform file trace.vcd will not be dumped and vice versa.

An example program to print HELLO on UART is compiled and its hex instructions are availabe in here. Run the folllowing command to simulate the example program

make sim-verilate 

This will simulate imem.txt and dump UART logs in uart_logdata.log. If vcd=1 is added to the above command, trace.vcd will created that can be viewed by running

gtkwave trace.vcd

The imem and max_cycles may be overwritten in Makefile using.

make sim-verilate imem=</path/to/hex/file> max_cycles=<No. of cycles> 

1.1.2. Verification

UETRV_Pcore uses RISOF framework to run Architecture Compatibility Tests (ACTs). Instructions to run these tests can be followed in verif directory.