Welcome to UETRV-PCore documentation!

Contents:

• 1. UETRV_Pcore: User Guide
  • 1.1. Getting Started
    • 1.1.1. Build Model and Run Simulation
    • 1.1.2. Verification
• 2. UETRV_Pcore: Design Document
  • 2.1. Introduction
    • 2.1.1. Key Features
    • 2.1.2. System Design Overview
    • 2.1.3. SoC Memory Map
  • 2.2. Design Details
    • 2.2.1. Instruction Fetch and Decode Stages
    • 2.2.2. Execute Stage and M-extension
    • 2.2.3. Memory and Writeback Stages
      • 2.2.3.1. A-extension
      • 2.2.3.2. CSR Module
    • 2.2.4. Pipeline Controller
    • 2.2.5. D-Cache
    • 2.2.6. I-Cache
    • 2.2.7. MMU Details
      • 2.2.7.1. PTW
      • 2.2.7.2. DTLB
      • 2.2.7.3. ITLB
    • 2.2.8. Booting and Peripherals